This invention relates to packaging microminiature devices and, more particularly, to a packaging assembly and a method in which one or more devices are affixed to and interconnected on a wafer.
Conventional integrated-circuit chip interconnection techniques involve the use of wire bonds between peripherally disposed pads on the chip and an associated lead frame that includes rigid terminal members. In turn, the lead frame is mounted in a chip package. The rigid terminals of one or more such packaged chips are then inserted into corresponding apertures in a ceramic board or card that contains a thin-film interconnection pattern.
An alternative packaging technique for achieving a very-high-density interconnection of active silicon-integrated-circuit devices without the use of wire bonds has been heretofore proposed. The alternative is directed at permitting the fabrication of large electronic subsystems in essentially monolithic form, as described, for example, in "Wafer-Chip Assembly for Large-Scale Integration," IEEE Transactions on Electron Devices, Vol. ED-15, No. 9, September 1968, pp. 660-663.
In the assembly described in the aforecited article, chips are face-down bonded onto a silicon wafer that contains interconnect lines. The same lithographic technology is used on the wafer as on the chips to obtain a very-high-packing density and a relatively low-inductance assembly. The face-down bonding permits access to each chip at points other than the periphery of the chip, thereby requiring only a relatively small part of the overall chip area for interconnect lines.
In the face-down bonding operation, conductive pads on each chip are bonded to corresponding pads included in the interconnect pattern on the wafer. To form such bonds between each chip and the wafer, a metallic bump is typically formed on the chip, or on the wafer, or on both. In practice, however, lack of uniformity in bump height and relatively poor long-term stability characteristics of the bump technology make this bonding approach unattractive for many high-reliability applications of practical importance. Moreover, the area required for the bumps on mating contact pads on the chip and wafer is extremely large relative to the micron and submicron dimensions that are becoming increasingly the goal of much integrated circuit design work.
In another known approach, flowable solder balls are utilized in a face-down bonding technique to form connections between chip and wafer pads. In practice, this approach tends to minimize the aforementioned problem of lack of uniformity in bump height. But this approach does not generally satisfy the goal of achieving extremely small-area connections between the chip and wafer pads.
For the aforestated reasons, workers in the art have continued their efforts directed at trying to further improve the packaging of integrated-circuit devices. It was recognized that these efforts, if successful, had the potential for significantly decreasing the cost and increasing the performance characteristics of such devices.